Ken Van Hoeylandt
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <assert.h>
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#include <sys/errno.h>
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#include "esp_idf_version.h"
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#include "esp_attr.h"
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#include "esp_heap_caps.h"
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#include "esp32s2/rom/cache.h"
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#if ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(5, 0, 0)
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#include "esp32s2/spiram.h"
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#endif
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#include "soc/mmu.h"
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#include "private/elf_platform.h"
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#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 0, 0)
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#define PSRAM_VADDR_START 0x3f800000
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#else
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#define PSRAM_VADDR_START (DRAM0_CACHE_ADDRESS_HIGH - esp_spiram_get_size())
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#endif
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#define MMU_INVALID BIT(14)
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#define MMU_UNIT_SIZE 0x10000
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#define MMU_REG ((volatile uint32_t *)DR_REG_MMU_TABLE)
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#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 2, 0)
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#define IRAM0_ADDRESS_LOW SOC_IRAM0_ADDRESS_LOW
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#define IRAM0_ADDRESS_HIGH SOC_IRAM0_ADDRESS_HIGH
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#define MMU_ACCESS_SPIRAM SOC_MMU_ACCESS_SPIRAM
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#endif
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#define ESP_MMU_IBUS_BASE IRAM0_ADDRESS_LOW
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#define ESP_MMU_IBUS_MAX ((IRAM0_ADDRESS_HIGH - IRAM0_ADDRESS_LOW) / \
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MMU_UNIT_SIZE)
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#define ESP_MMU_IBUS_OFF (8)
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#define DADDR_2_SECS(v) ((v) / MMU_UNIT_SIZE)
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#define IADDR_2_SECS(v) ((v) / MMU_UNIT_SIZE)
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#define PSRAM_OFF(v) ((v) - PSRAM_VADDR_START)
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#define PSRAM_SECS(v) DADDR_2_SECS(PSRAM_OFF((uintptr_t)(v)))
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#define PSRAM_ALIGN(v) ((uintptr_t)(v) & (~(MMU_UNIT_SIZE - 1)))
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#define ICACHE_ADDR(s) (ESP_MMU_IBUS_BASE + (s) * MMU_UNIT_SIZE)
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extern void spi_flash_disable_interrupts_caches_and_other_cpu(void);
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extern void spi_flash_enable_interrupts_caches_and_other_cpu(void);
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/**
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* @brief Initialize MMU hardware remapping function.
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*
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* @param elf - ELF object pointer
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*
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* @return 0 if success or a negative value if failed.
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*/
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int IRAM_ATTR esp_elf_arch_init_mmu(esp_elf_t *elf)
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{
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int ret;
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int off;
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uint32_t ibus_secs;
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volatile uint32_t dbus_secs;
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esp_elf_sec_t *sec = &elf->sec[ELF_SEC_TEXT];
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volatile uint32_t *p = MMU_REG;
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if (sec->size % MMU_UNIT_SIZE) {
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ibus_secs = IADDR_2_SECS(sec->size) + 1;
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} else {
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ibus_secs = IADDR_2_SECS(sec->size);
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}
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dbus_secs = PSRAM_SECS(elf->ptext);
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spi_flash_disable_interrupts_caches_and_other_cpu();
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for (off = ESP_MMU_IBUS_OFF; off < ESP_MMU_IBUS_MAX; off++) {
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if (p[off] == MMU_INVALID) {
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int j;
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for (j = 1; j < ibus_secs; j++) {
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if (p[off + j] != MMU_INVALID) {
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break;
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}
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}
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if (j >= ibus_secs) {
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for (int k = 0; k < ibus_secs; k++) {
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p [off + k] = MMU_ACCESS_SPIRAM | (dbus_secs + k);
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}
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break;
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}
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}
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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if (off >= ESP_MMU_IBUS_MAX) {
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ret = -EIO;
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} else {
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elf->mmu_off = off;
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elf->mmu_num = ibus_secs;
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elf->text_off = ICACHE_ADDR(off) - PSRAM_ALIGN(elf->ptext);
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ret = 0;
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}
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return ret;
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}
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/**
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* @brief De-initialize MMU hardware remapping function.
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*
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* @param elf - ELF object pointer
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*
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* @return None
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*/
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void IRAM_ATTR esp_elf_arch_deinit_mmu(esp_elf_t *elf)
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{
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volatile int num = elf->mmu_num;
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volatile int off = elf->mmu_off;
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volatile uint32_t *p = MMU_REG;
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spi_flash_disable_interrupts_caches_and_other_cpu();
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for (int i = 0; i < num; i++) {
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p [off + i] = MMU_INVALID;
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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}
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