Ken Van Hoeylandt
124 lines
4.1 KiB
YAML
124 lines
4.1 KiB
YAML
description: >
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Sitronix ST7123 MIPI-DSI display panel, driven over ESP-IDF's esp_lcd_st7123 component
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(DPI/DBI interface, ESP32-P4 and other SOC_MIPI_DSI_SUPPORTED targets only). Owns the MIPI DSI
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PHY LDO channel and DSI bus directly, so unlike SPI/RGB panels it has no parent bus controller
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device.
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compatible: "sitronix,st7123"
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properties:
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horizontal-resolution:
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type: int
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required: true
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description: Horizontal resolution in pixels
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vertical-resolution:
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type: int
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required: true
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description: Vertical resolution in pixels
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bits-per-pixel:
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type: int
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default: 16
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description: Color depth in bits per pixel (16, 18 or 24)
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bgr-order:
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type: boolean
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default: false
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description: Use BGR element order instead of RGB
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invert-color:
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type: boolean
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default: false
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description: Invert the panel's color output
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mirror-x:
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type: boolean
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default: false
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description: Mirror the X axis
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mirror-y:
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type: boolean
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default: false
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description: Mirror the Y axis
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pin-reset:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Reset GPIO pin. Falls back to a software reset (sent over the DBI command
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interface) if not set.
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ldo-channel:
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type: int
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required: true
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description: LDO channel index powering the MIPI DSI PHY (chan_id in esp_ldo_channel_config_t)
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ldo-voltage-mv:
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type: int
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required: true
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description: Voltage to supply to the MIPI DSI PHY LDO channel, in mV
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dsi-bus-id:
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type: int
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default: 0
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description: Which DSI controller to use, index from 0
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num-data-lanes:
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type: int
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default: 2
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description: Number of MIPI DSI data lanes. 0 falls back to the maximum available.
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lane-bit-rate-mbps:
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type: int
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required: true
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description: MIPI DSI lane bit rate, in Mbps
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dpi-clock-freq-mhz:
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type: int
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required: true
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description: MIPI DPI clock frequency, in MHz
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hsync-pulse-width:
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type: int
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required: true
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description: Horizontal sync width, in PCLK periods
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hsync-back-porch:
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type: int
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required: true
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description: Number of PCLK periods between hsync and the start of line active data
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hsync-front-porch:
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type: int
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required: true
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description: Number of PCLK periods between the end of active data and the next hsync
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vsync-pulse-width:
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type: int
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required: true
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description: Vertical sync width, in lines
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vsync-back-porch:
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type: int
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required: true
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description: Number of invalid lines between vsync and the start of the frame
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vsync-front-porch:
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type: int
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required: true
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description: Number of invalid lines between the end of the frame and the next vsync
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num-fbs:
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type: int
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default: 1
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description: Number of screen-sized frame buffers to allocate (0 or 1 = single-buffered)
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use-dma2d:
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type: boolean
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default: true
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description: Use DMA2D to copy user buffers into the frame buffer when necessary (only
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meaningful on SOC_DMA2D_SUPPORTED targets - must be false otherwise)
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disable-lp:
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type: boolean
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default: false
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description: Disable MIPI DSI low-power mode
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allow-tearing:
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type: boolean
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default: false
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description: By default, when draw_bitmap's color_data is one of the panel's own frame
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buffers (i.e. LVGL is bound directly onto them), draw_bitmap waits for a full scan-out to
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complete before returning so the caller can't start overwriting a buffer still being
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displayed. Set this to trade away that tear-free guarantee for lower latency (e.g. when
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other tasks occasionally block timing for long enough that waiting causes visible stalls).
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init-sequence:
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type: array
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element-type: uint8_t
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description: >
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Custom vendor bring-up sequence, flattened into bytes as a run of
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[cmd, data-length, delay-ms, data-length bytes of data...] entries, e.g.
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`init-sequence = [0x11 0 120 0x29 0 20];`.
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Omit to use the ST7123 component's own built-in default sequence.
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backlight:
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type: phandle
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default: "NULL"
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description: Optional reference to this display's backlight device
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