Update ST7305 display driver initialization to match rlcd.py settings

This commit is contained in:
Adolfo Reyna
2026-07-09 23:09:13 -04:00
parent b5f0575c5c
commit da28b93f24
+5 -5
View File
@@ -46,12 +46,12 @@ static const st7305_lcd_init_cmd_t st7305_init_cmds[] = {
{0xD6, (uint8_t[]){0x17, 0x02}, 2, 0}, // NVM Load Control
{0xD1, (uint8_t[]){0x01}, 1, 0}, // Booster Enable
{0xC0, (uint8_t[]){0x11, 0x04}, 2, 0}, // Gate Voltage Setting
{0xC1, (uint8_t[]){0x69, 0x69, 0x69, 0x69}, 4, 0}, // VSHP Setting
{0xC1, (uint8_t[]){0x41, 0x41, 0x41, 0x41}, 4, 0}, // VSHP Setting
{0xC2, (uint8_t[]){0x19, 0x19, 0x19, 0x19}, 4, 0}, // VSLP Setting
{0xC4, (uint8_t[]){0x4B, 0x4B, 0x4B, 0x4B}, 4, 0}, // VSHN Setting
{0xC5, (uint8_t[]){0x19, 0x19, 0x19, 0x19}, 4, 0}, // VSLN Setting
{0xD8, (uint8_t[]){0x80, 0xE9}, 2, 0}, // OSC Setting
{0xB2, (uint8_t[]){0x02}, 1, 0}, // Frame Rate Control
{0xC4, (uint8_t[]){0x41, 0x41, 0x41, 0x41}, 4, 0}, // VSHN Setting
{0xC5, (uint8_t[]){0x19, 0x13, 0x19, 0x19}, 4, 0}, // VSLN Setting
{0xD8, (uint8_t[]){0xA6, 0xE9}, 2, 0}, // OSC Setting
{0xB2, (uint8_t[]){0x05}, 1, 0}, // Frame Rate Control
{0xB3, (uint8_t[]){0xE5, 0xF6, 0x05, 0x46, 0x77, 0x77, 0x77, 0x77, 0x76, 0x45}, 10, 0}, // Gate EQ HPM
{0xB4, (uint8_t[]){0x05, 0x46, 0x77, 0x77, 0x77, 0x77, 0x76, 0x45}, 8, 0}, // Gate EQ LPM
{0x62, (uint8_t[]){0x32, 0x03, 0x1F}, 3, 0}, // Gate Timing Control