Device migrations and driver implementations (#564)
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Ken Van Hoeylandt
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GitHub
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description: >
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ESP32 RGB (parallel timing-driven) LCD panel, built on ESP-IDF's esp_lcd_rgb_panel
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component. Unlike SPI/i8080 panels, an RGB panel has no command interface and owns its
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GPIOs directly rather than sitting behind a shared bus controller device.
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compatible: "espressif,esp32-rgb-display"
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properties:
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horizontal-resolution:
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type: int
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required: true
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description: Horizontal resolution in pixels
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vertical-resolution:
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type: int
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required: true
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description: Vertical resolution in pixels
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pixel-clock-hz:
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type: int
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required: true
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description: Pixel clock frequency in Hz
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hsync-pulse-width:
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type: int
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required: true
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description: Horizontal sync width, in PCLK periods
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hsync-back-porch:
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type: int
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required: true
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description: Number of PCLK periods between hsync and the start of line active data
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hsync-front-porch:
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type: int
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required: true
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description: Number of PCLK periods between the end of active data and the next hsync
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vsync-pulse-width:
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type: int
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required: true
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description: Vertical sync width, in lines
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vsync-back-porch:
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type: int
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required: true
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description: Number of invalid lines between vsync and the start of the frame
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vsync-front-porch:
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type: int
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required: true
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description: Number of invalid lines between the end of the frame and the next vsync
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hsync-idle-low:
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type: boolean
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default: false
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description: The hsync signal is low in the idle state
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vsync-idle-low:
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type: boolean
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default: false
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description: The vsync signal is low in the idle state
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de-idle-high:
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type: boolean
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default: false
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description: The DE signal is high in the idle state
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pclk-active-neg:
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type: boolean
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default: false
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description: Whether display data is clocked out on the falling edge of PCLK
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pclk-idle-high:
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type: boolean
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default: false
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description: The PCLK signal stays high in the idle phase
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data-width:
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type: int
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default: 16
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description: Number of parallel data lines wired (8 or 16)
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bits-per-pixel:
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type: int
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default: 0
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description: Frame buffer color depth in bpp. 0 defaults to data-width.
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num-fbs:
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type: int
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default: 1
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description: Number of screen-sized frame buffers to allocate (0 or 1 = single-buffered)
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bounce-buffer-size-px:
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type: int
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default: 0
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description: Non-zero enables the DRAM bounce-buffer DMA path, sized in pixels
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sram-trans-align:
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type: int
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default: 8
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description: Alignment of buffers allocated in internal SRAM
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psram-trans-align:
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type: int
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default: 64
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description: Alignment of buffers allocated in PSRAM
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pin-hsync:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: HSYNC GPIO pin, optional for panels that only need DE (data-enable) sync
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pin-vsync:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: VSYNC GPIO pin, optional for panels that only need DE (data-enable) sync
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pin-de:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data-enable GPIO pin, optional
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pin-pclk:
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type: phandles
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required: true
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description: Pixel-clock GPIO pin
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pin-disp:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Optional display-enable control GPIO pin
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pin-reset:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Optional hardware reset pin for the panel's own driver IC, pulsed once at start()
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reset-active-high:
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type: boolean
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default: false
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description: Whether the reset pin is active high
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pin-data0:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 0 GPIO pin
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pin-data1:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 1 GPIO pin
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pin-data2:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 2 GPIO pin
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pin-data3:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 3 GPIO pin
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pin-data4:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 4 GPIO pin
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pin-data5:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 5 GPIO pin
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pin-data6:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 6 GPIO pin
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pin-data7:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 7 GPIO pin
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pin-data8:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 8 GPIO pin
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pin-data9:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 9 GPIO pin
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pin-data10:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 10 GPIO pin
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pin-data11:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 11 GPIO pin
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pin-data12:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 12 GPIO pin
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pin-data13:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 13 GPIO pin
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pin-data14:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 14 GPIO pin
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pin-data15:
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type: phandles
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default: GPIO_PIN_SPEC_NONE
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description: Data bus bit 15 GPIO pin
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disp-active-low:
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type: boolean
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default: false
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description: A low level on the display-enable control signal turns the screen on
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refresh-on-demand:
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type: boolean
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default: false
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description: Only refresh the frame buffer on explicit draw_bitmap calls
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fb-in-psram:
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type: boolean
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default: true
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description: Allocate the frame buffer from PSRAM, preferentially
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double-fb:
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type: boolean
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default: false
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description: Allocate two screen-sized frame buffers (equivalent to num-fbs = 2)
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no-fb:
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type: boolean
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default: false
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description: Don't allocate a frame buffer; bounce buffer must be filled manually
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bb-invalidate-cache:
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type: boolean
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default: false
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description: Invalidate cache on bounce-buffer reads (can be dangerous with multi-core writers)
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swap-xy:
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type: boolean
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default: false
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description: Swap the X and Y axes
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mirror-x:
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type: boolean
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default: false
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description: Mirror the X axis
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mirror-y:
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type: boolean
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default: false
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description: Mirror the Y axis
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invert-color:
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type: boolean
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default: false
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description: Invert the panel's color output
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backlight:
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type: phandle
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default: "NULL"
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description: Optional reference to this display's backlight device
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