GPIO refactored (#495)
* **Refactor** * GPIO subsystem moved to a descriptor-based model for per-pin ownership and runtime pin management; many platform drivers now acquire/release descriptors. * Device trees and drivers now use GPIO phandle-style pin specifications across all boards and all drivers. * **Behavior** * Device list now encodes per-device status (ok/disabled); boot will skip disabled devices accordingly. * **Deprecation** * Legacy GPIO HAL marked deprecated and replaced with descriptor-based interfaces. * **Chores** * Bindings and platform configs updated to the new GPIO pin-spec format.
This commit is contained in:
committed by
GitHub
parent
dff93cb655
commit
26c17986c6
@@ -16,14 +16,8 @@ properties:
|
||||
required: true
|
||||
description: Initial clock frequency in Hz
|
||||
pin-sda:
|
||||
type: int
|
||||
type: phandle-array
|
||||
required: true
|
||||
pin-scl:
|
||||
type: int
|
||||
type: phandle-array
|
||||
required: true
|
||||
pin-sda-pull-up:
|
||||
type: bool
|
||||
description: enable internal pull-up resistor for SDA pin
|
||||
pin-scl-pull-up:
|
||||
type: bool
|
||||
description: enable internal pull-up resistor for SCL pin
|
||||
|
||||
@@ -12,23 +12,22 @@ properties:
|
||||
The port number, defined by i2s_port_t.
|
||||
Depending on the hardware, these values are available: I2S_NUM_0, I2S_NUM_1
|
||||
pin-bclk:
|
||||
type: int
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: BCK pin
|
||||
description: Bit clock pin
|
||||
pin-ws:
|
||||
type: int
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: WS pin
|
||||
description: Word (slot) select pin
|
||||
pin-data-out:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
description: DATA OUT pin
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: Data output pin
|
||||
pin-data-in:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
description: DATA IN pin
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: Data input pin
|
||||
pin-mclk:
|
||||
type: int
|
||||
required: false
|
||||
default: GPIO_PIN_NONE
|
||||
description: MCLK pin
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: Master clock pin
|
||||
|
||||
@@ -11,25 +11,24 @@ properties:
|
||||
description: |
|
||||
The SPI host (controller) to use.
|
||||
Defined by spi_host_device_t (e.g. SPI2_HOST, SPI3_HOST).
|
||||
pin-sclk:
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
pin-mosi:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: MOSI (Data 0) pin
|
||||
pin-miso:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: MISO (Data 1) pin
|
||||
pin-sclk:
|
||||
type: int
|
||||
required: true
|
||||
description: Clock pin
|
||||
pin-wp:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: WP (Data 2) pin
|
||||
pin-hd:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: HD (Data 3) pin
|
||||
max-transfer-size:
|
||||
type: int
|
||||
|
||||
@@ -12,18 +12,18 @@ properties:
|
||||
The port number, defined by uart_port_t.
|
||||
Depending on the hardware, these values are available: UART_NUM_0, UART_NUM_1, UART_NUM_2
|
||||
pin-tx:
|
||||
type: int
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: TX pin
|
||||
pin-rx:
|
||||
type: int
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: RX pin
|
||||
pin-cts:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: CTS pin
|
||||
pin-rts:
|
||||
type: int
|
||||
default: GPIO_PIN_NONE
|
||||
type: phandle-array
|
||||
default: GPIO_PIN_SPEC_NONE
|
||||
description: RTS pin
|
||||
|
||||
Reference in New Issue
Block a user